Power Minimization Problems of Logic Networks

As a method for greatly reducing power dissipation in logic networks, we propose some logic organization techniques for logic networks. By such techniques, their power dissipation is to be minimized under certain input conditions, or the average power dissipation in the whole network should be minimized. A logic network in which these problems are taken into account will be called a power minimized logic circuit (PML). In this paper, using so-called asymmetrically power dissipating elements in which power dissipation varies with on-off conditions, it is shown that it is possible to considerably reduce power dissipation in logic networks by only utilzing logic organization methods. First the power minimization problem of logic networks under certain fixed input conditions is discussed. Next a method is presented for synthesizing a PML with asymmetrically power dissipating NAN) elements, and it is proved that the PML synthesized by this method satisfies the minimum value of power dissipation under all input conditions. The minimum number of gates dissipating higher power in an arbitrary singleoutput combinatorial logic network -is zero or one when the output is 1, and one or two when it is 0. The average power dissipation of this PML is always theoretically minimal, independent of the occurrence probabilities of input conditions. In practice, the number of gates would hardly increase very much. The use of a PML is compatible with the use of low-power logic elements.